[to index] | [close window] | [C_RIND Verification]

# Coplanar Rectangular Inductor C_RIND

### Symbol :

### Illustration :

### Parameters :

> L1 = Length of transmission line section connected with the coplanar inductor at port 1
> L2 = Length of transmission line section connected with the coplanar inductor at port 2
> N = Number of turns (positive ® contra clock wise, negative ® clock wise)
> WT = Track width
> ST = Slot between tracks
> I_DIA1 = Inner diameter 1
> I_DIA2 = Inner diameter 2
> S = Slot between track and ground
> INDLEVEL = Identification of metal level of inductor turns
> C_LTYP1 = ID of coplanar transmission line applied at port 1 (backtrack)
> C_LTYP2 = ID of coplanar transmission line applied at port 2
> C_BTR = ID of backtrack-bridge
> C_SUB = ID of coplanar substrate definition
> C_GRID = ID of simulation control data
> TEMP = ID of element temperature definition used for noise computation

### Range of Usage :

> N = 1.5, 2.5, 3.5, ... (-1.5, -2.5, -3.5, ...)
> WT = 0.5.n.DL* n=1,2,3,...
> ST = 0.5.n.DL* n=1,2,3,...
> I_DIA1 = 0.5.n.DL* n=1,2,3,... (I_DIA1 ³ ST)
> I_DIA2 = 0.5.n.DL* n=1,2,3,...
> S = 0.5.n.DL* n=1,2,3,...
> * ) see C_GRID for information on DL

### Notes/Equations/References :

> 1. The C_RIND module represents a rectangular spiral inductor two coplanar lines. The dimensions of lines are defined using data items addressed by C_ LTYP1 and C_LTYP2 (see C_LINTYP in chapter 4).
> 2. A negative value for L1 or L2 can be meaningful during the simulation. In such cases, the automated layout generation works incorrectly and the generated layout has to be edited manually. The minimum values for L1 or L2 depend on the metal layer oversizes in the currently selected foundry. In case of C_LAYER_DEFAULT, L1 and L2 should be greater than or equal to max(|cond_os|, |cond2_os|).
> 3. I_DIA1 must be greater than or equal ST.
> 4. I_DIA2 must be greater than or equal to via_ol–WT.
> 5. The minimum value for N is 1.5 and the increment is 1. Negative value for N (-1.5, -2.5, -3.5 ...) indicates the turn direction in clock wise and positive value in contra clock wise (see Layout). The sign of N has no effect on simulation.
> 6. TYPE=0 and TYPE= –1 is not allowed in C_AIRTYP addressed by C_BTR.
> 7. The only valid value for INDLEVEL in DEFAULT foundry is 1 or 2.
> 8. If the length of connected line to port1 is less than via_ol (see C_LAYER), CEN_MET in C_LTYP1 must be the same as TYPE in C_BTR.
> 9. INDLEVEL and TYPE in C_AIRTYP addressed by C_BTR must be different.
> 10. If L1 and L2 in selected C_GRID are not set to -1 (auto sizing), the minimum values for L1 and L2 are:
>     L1min= max(WT+(WT+ST)*(2*N-1)-ST+IDIA1+2*S+8*DL{C_GRID}, W1+2*S1+2*GW1,W2+2*S2+2*GW2)
>     L2min= 2*WT+(WT+ST)*(2*N-1)+IDIA2+2*S+8*DL{C_GRID}
> 11. See notations in chapter 4 (Important Note!) for the correct selection of the C_LTYP1 and C_LTYP2.

### Equivalent Circuit :

> For the modeling of the C_RIND element, a broadband network is used. The equivalent circuit parameters are derived from quasi-static FD-calculations. Since for every segment (straight line sections within turns) a p-network is used, the traveling wave effects within the turns are considered. The connected line at ports are modeled as C_LIN elements and are represented by their characteristic impedance ZL and phase constant b. There is no limitation due to the length of connected lines (L1 and L2)

### Layout :

> 1. The turns of inductor can be realized in different metal level.
> 2. If CEN_MET in C_LTYP1 and TYPE in C_BTR are different, an inter metal via is automatically included at port 1. In this case the length of connected line at port 1 must be at least via_lo in C_LAYER.
> 3. If the parameter GW_DEF in C_PROCES is set to a positive non-zero value, this value is used as ground width for layout generation. In this case the length of connected lines have to be greater than zero.

[to index] | [close window] | [C_RIND Verification]