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# Coplanar Step C_STEP

### Symbol :

### Illustration :

### Parameters :

> L1 = Length of transmission line connected to the port 1.
> L2 = Length of transmission line connected to the port 2.
> SL = Step Length
> C_LTYP1 = ID of coplanar transmission line applied at port 1
> C_LTYP2 = ID of coplanar transmission line applied at port 2
> C_SUB = ID of coplanar substrate definition
> C_GRID = ID of simulation control data
> TEMP = ID of element temperature definition used for noise computation

### Range of Usage :

SL = 0.5.n.DL* n=1,2,3,...
* ) see C_GRID for information on DL

### Notes/Equations/References :

> 1. The C_STEP module represents a step in line width and/or line slot of a coplanar line. The dimensions of lines at both sides of a step are defined using data items addressed by C_ LTYP1 and C_TYP2. SL is the step length. L1 and L2 are the lengths of connected coplanar lines at ports.
> 2. A negative value for L1 or L2 can be meaningful during the simulation. In such cases, the automated layout generation works incorrectly and the generated layout has to be edited manually. The minimum values for L1 or L2 depend on the metal layer oversizes in the currently selected C_LAYER. In case of DEFAULT foundry, L1 and L2 should be greater than or equal to max(|cond_os|, |cond2_os|).
> 3. C_LTYP1 and C_TYP2 must have the same CEN_MET and GND_MET.
> 4. A value of SL=0 is not possible, if W1+2S1 £ W2 (or W2+2S2 £ W1).
> 5. The difference between the center line widths (W2-W1) has to be an integer multiple of DL. Otherwise the simulator will shift the line at port 1 by a half of grid size (DL/2). In this case the step will become asymmetrical and the user get the message: “(W2-W1)/DL no integer ® asymmetrical step”. Please not that this change is not considered by layout generation. The layout of a step is always symmetrical.
> 6. If W1+2S1+2GW1 ¹ W2+2S2+2GW2, there could be an step in the outer contour of the ground strips. In this case, the ground width of the line with smaller value of W+2S+2GW is increased (see layout), so that there is no step in the outer contour of ground planes. This change is considered by the simulation and layout generation.
> 7. If W1<W2 and W1+2S1>W2+2S2 (or W2>W1 and W1+2S1<W2+2S2), the step in the inner contour of ground planes is shifted by SL (see layout). This change is considered by the simulation.
> 8. If L1 and L2 in selected C_GRID are not set to –1 or –2 (auto sizing), the minimum values for L1 and L2 are:
>    L1min=max( W1+2*S1+2*GW1, W2+2*S2+2*GW2)
>    L2min=8*DL{C_GRID}+SL
> 9. See notations in chapter 4 (Important Note!) for the correct selection of the C_LTYP1, C_LTYP2.

### Equivalent Circuit :

> For the modeling of the C_STEP element, a p-network is used. The equivalent circuit parameters are derived from electric quasi-static FD-calculations. The connected line at ports are modeled as C_LIN elements and are represented by their characteristic impedance ZL and phase constant b. There is no limitation due to the length of connected lines (L1 and L2).

### Layout :

> 1. If W1+2S1+2GW1 ¹ W2+2S2+2GW2, the ground width of the line with smaller value of W+2S+2GW is changed (no step in the outer contour of ground planes).
> 2. If W1+2S1 > W2+2S2, the step in the ground planes is shifted by SL. In this case, the step is an extension of the line with the smaller center line width.
> 3. If the parameter GW_DEF in C_PROCES is set to a positive non-zero value, this value is used as ground width for layout generation

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