[to index] | [close window] | [C_IDC Verification]

# Coplanar Interdigital Capacitor C_IDC

### Symbol :

### Illustration :

### Parameters :

> L1 = Length of transmission line connected with the coplanar capacitor at port 1
> L2 = Length of transmission line connected with the coplanar capacitor at port 2.
> WF = Width of fingers
> SF = Slot between fingers
> LF = Length of fingers
> NF = Number of fingers (>1)
> S = Slot between ground and fingers
> G = Gap between ground and feed line
> WL = Length of feed line
> IDCLEVEL = Identification of metal level of the interdigital section
> C_LTYP1 = ID of coplanar transmission line applied at port 1
> C_LTYP2 = ID of coplanar transmission line applied at port 2 (=C_LTYP1 for simulation)
> C_SUB = ID of coplanar substrate definition
> C_GRID = ID of simulation control data
> TEMP = ID of element temperature definition used for noise computation

### Range of Usage :

> WF = 0.5.n.DL* n=1,2,3,...
> SF = 0.5.n.DL* n=1,2,3,...
> LF = 0.5.n.DL* n=2,3,4,... (LF > SF)
> NF = n n=2,3,4,...
> S = 0.5.n.DL* n=1,2,3,...
> G = 0.5.n.DL* n=1,2,3,...
> WL = 0.5.n.DL* n=1,2,3,...
> * ) see C_GRID for information on DL

### Notes/Equations/References :

> 1. The C_IDC module represents an interdigitated capacitor between center conductor of two coplanar lines. The dimensions of lines are defined using data items addressed by C_ LTYP1 and C_LTYP2 (see C_LINTYP in chapter 4).
> 2. L1 and L2 are the length of coplanar lines connected at ports.
> 3. A negative value for L1 or L2 can be meaningful during the simulation. In such cases, the automated layout generation works incorrectly and the generated layout has to be edited manually. The minimum values for L1 or L2 depend on the metal layer oversizes in the currently selected foundry. In case of C_LAYER_DEFAULT, L1 and L2 should be greater than or equal to max(|cond_os|, |cond2_os|).
> 4. WF is the width of fingers and SF is the distance between the fingers. As shown in the Illustration, the gap at end of fingers is equal to the slots between the fingers.
> 5. LF is the length of the fingers (without the slot at the end of fingers). LF should always be greater than SF.
> 6. NF is the number of fingers and has to be an integer number. The minimum value for NF is 2. Note that for odd numbers of NF, the number of fingers connected to port one is greater than the number of fingers connected to port 2.
> 7. S is the slot between fingers and the ground planes. This parameter influences the parasitic capacitances to the ground (Cp1 and Cp2).
> 8. G is the gap between the ground planes and the feed lines connected to the fingers. <0, the automated layout generation works incorrectly and the generated layout has to be edited manually.
> 9. WL is the length of feed lines connected to the fingers.
> 10. The parameter IDCLEVEL indicates the metal level used for the interdigitated capacitor. The only valid value for this parameter in the DEFAULT foundry is 1 or 2.
> 11. If IDCLEVEL and CEN_MET of connected lines are different, an inter metal via is automatically included at the ports. In this case the length of connected lines must at least via_lo in C_LAYER
> 12. In the current version, the same C_LTYP is applied at both ports for the simulation (C_LTYP2 = C_LTYP1).
> 13. If L1 and L2 in selected C_GRID are not set to -1 (auto sizing), the minimum values for L1 and L2 are:
>     L1min= max(NF*WF+(NF-1)*SF+2*S+8*DL{C_GRID}, W1+2*S1+2*GW1,W2+2*S2+2*GW2)
>     L2min= LF+SF+2*WL+2*G+8*DL{C_GRID}
> 14. See notations in chapter 4 (Important Note!) for the correct selection of the C_LTYP1 and C_LTYP2.

### Equivalent Circuit :

> For the modeling of the C_IDC element, a broadband network is used. The equivalent circuit parameters are derived from quasi-static FD-calculations. The traveling wave effects along the fingers is taken into account. As a result, there is no limitation due to the length of fingers. The connected line at ports are modeled as C_LIN elements and are represented by their characteristic impedance ZL and phase constant b. There is no limitation due to the length of connected lines (L1 and L2).

### Layout :

> 1. Two different metal level can be used for the fingers of an interdigital capacitors.
> 2. If IDCLEVEL and CEN_MET of connected lines are different, an inter metal via is automatically included at the ports. In this case the length of connected lines must be at least via_lo in C_LAYER.
> 3. If the parameter GW_DEF in C_PROCES is set to a positive non-zero value, this value is used as ground width for layout generation.

[to index] | [close window] | [C_IDC Verification]