From our founding 15 years ago, we have been involved in leading-edge algorithms and digital hardware design. Today, we are an experienced and highly skilled team with a mature design-flow and an extensive IPR-library. We have worked in both public and private partnership projects in telecommunications, system design, digital signal processing, and digital hardware design. The range and depth of our experience are unique. In the past, our work on these challenging and diverse projects has not been directly visible because our technology has been integrated into larger systems.

All that has changed! We now offer design services and off-the-shelf IP-cores as commercially available products. Today, you can also get directly in touch with our development team for greater efficiency, less chance for error, and timely, cost-efficient system designs - all by accessing this IPR-library online. Our new design-flow is highly integrated and consists of widely-deployed design, simulation and infrastructural tools that automatically cross-verify every step of the design. Our teams are efficient and provide extensive documentation support. Supported languages and tools include VHDL, C, C++, Assembler, Matlab™, Visual Elite™, ModelSim™, ISE Design Suite™, SVN, and Doxygen.

Why re-invent the wheel? IMST has created an extensive library of VHDL-based IP-blocks with flexible programming. Testing is conducted automatically by both simulation and hardware (FPGA) in the loop to ensure that each IP-block retains its integrity with every extension of the code. IMST is now making its library available commercially as DSPware. Clients can purchase individual IP blocks or the entire library when our dedicated web-portal is launched in Q1 of 2010. The site will offer the latest versions, technical support, and up-to-date documentation.

As an indication of what to expect, a preliminary library list is appended below containing a subset of IP cores. Some cores are available for free download after registration with sometimes limited generic parameter ranges. Please contact us if you require different settings or if you are interested in advanced cores like the Viterbi decoder or the sorting algorithms.

Do you have questions or comments? Please contact us!

Module	Description	Download
Viterbi_Dec	Configurable Viterbi decoder	Data sheet
ConvEnc	Configurable convolutional encoder	Data sheet
Sqrt_SLV	Fast iterative square root algorithm	Data sheet
Div_SLV	Fast iterative integer division	Data sheet
Stream_Sort_SLV	Sorting algorithm on an input data stream (sliding window)	Data sheet
WGN_SLV	White gaussian noise source	Data sheet